8. Initialization

8.2 Power-On Reset Sequence

• The external agent negates DCOk.
• The external agent asserts SysReset*.
• The external agent negates SysGnt*.
• The external agent negates SysRespVal*.
• Once Vcc, VccQ[SC,Sys], Vref[SC,Sys], Vcc[Pa,Pd], and SysClk stabilize, the external agent waits at least 1ms and then asserts DCOk.
• At this time, the System interface resides in slave state and all internal state is initialized.
• The SysClkDiv mode bits default to divide-by-1.
• The SCClkDiv mode bits default to divide-by-3.
• After waiting at least 100 ms for the internal clocks to stabilize, the external agent loads the mode bits into the processor by driving the mode bits on SysAD[63:0], waiting at least two SysClk cycles, and then asserting SysGnt* for at least one SysClk cycle.
• After waiting at least another 100 ms for the internal clocks to restabilize, the external agent synchronizes all clocks internal to the processor. This is performed by asserting SysRespVal* for one SysClk cycle.
• After waiting at least 100 ms for the internal clocks to again restabilize, (a third 100 ms restabilization period) the external agent negates SysReset*.
• The external agent must retain mastership of the System interface, refrain from issuing external requests or nonmaskable interrupts, and ignore the system state bus until the processor asserts SysReq*. The assertion of SysReq* indicates the processor is ready for operation. In a cluster arrangement, all processors must assert SysReq*, indicating they are ready for operation.

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Figure 8-1 shows the Power-on Reset sequence.

Figure 8-1 Power-On Reset Sequence